The technical field relates generally to digital computer systems. More particularly, it relates to a method and an apparatus for processing branching instructions in a processor.
Typical computer systems have a number of common components. These components include a central processing unit (CPU), a bus, memory, and peripheral devices. In high-speed computers, the CPU may be a superscalar, pipelined microprocessor. A superscalar, pipelined microprocessor can include an instruction fetch unit and multiple pipelines. The instruction fetch unit fetches instructions and forwards them to a pipeline. In the pipeline, the instructions flow through multiple pipeline stages, after which the results of the instructions are committed to an architectural state (i.e., memory).
A pipelined microprocessor performs parallel processing in which instructions are executed in an assembly-line fashion. Consecutive instructions are operated upon in sequence, but several instructions are initiated before a first instruction is complete. In this manner, instructions step through each stage of a particular pipeline, one instruction per stage per pipeline at a time.
With respect to instructions processed by a pipeline, methods exist by which data and control functions are speculated. These methods also include means by which the control- or data-speculative calculation is checked for success or failure using a speculation check instruction, also referred to as xe2x80x9cchkxe2x80x9d instruction. The speculation check instruction checks for a certain condition in the instruction stream. If that condition fails, then the system branches to the target specified in the chk instruction. Existing methods, however, do not efficiently handle mis-speculation. In existing methods, if the speculation fails, the system does not implement the branching behavior defined by the IA-64 architecture. Instead, existing methods handle the failing speculation check instruction through software, rather than using the hardware. These methods cause a fault and invoke a fault handler, which emulates the branching behavior, rather than using hardware to resteer the instruction stream. However, treating exceptions through the fault handler is inefficient.
What is needed is a method for implementing a resteer upon the occurrence of a failing speculation check instruction, rather than faulting to improve performance. In particular, it is desirable to implement a resteer method that substantially uses preexisting hardware to further increase efficiency.
A method and an apparatus for resteering failing speculation check instructions in the pipeline of a processor. A branch offset immediate value and an instruction pointer correspond to each speculation check instruction. These values are used to determine the correct recovery target address. A relative adder adds the immediate value and the instruction pointer value to arrive at the correct address. This is done by flushing the pipeline upon the occurrence of a failing speculation check instruction. The pipeline flush is extended to resteer the machine to the recovery target address. The immediate value and the instruction pointer are then routed through the existing data paths of the pipeline, into the relative adder, which calculates the recovery target address. A sequencer tracks the progression of these values through the pipeline and effects a branch at the desired time.
The system may be optionally unimplemented by setting it to fault upon the occurrence of a failing speculation check instruction rather than initiating a branch resteer. If the fault is triggered, then a fault handler is invoked and uses software to emulate the branch. Also, the system may be set to operate only if it is first determined that the branch will actually arrive at its destination. This is done by ensuring that certain faults will not prevent a branch.